Software Architect for digital event driven simulation of Verilog, VHDL, SystemC, and e languages. Specializing in high performance scalable solutions to meet the market demand of IP driven SoC design and verification needs. Will design new algorithms and techniques to implement event driven simulation, build prototypes that demonstrate functionality, and lead large geographically disperse teams of engineers to implement, productize, and maintain the core simulation engine.
BSEE/CS degree with 10 years experience or MSEE/CS or PhD with 7 years experience.
Parallel programming experience on multiple cores required.
C/C++ programming experience is required.
Good written and oral communication skills and English language proficiency is expected.
Experience with Cloud Computing and/or GPU programming is advantageous.
Detailed knowledge of the Verilog and SystemVerilog languages with working knowledge of VHDL desired.
Experience with event driven HDL simulation techniques will be useful.
Experience building parsers, compilers, or with data structure generation is valuable.
Project lead experience for teams with more than 10 people will be helpful.
Knowledge of other programming languages including Java, Erlang, TCL/TK, Perl, or Unix Shell scripting is a plus.
Position requires quarterly travel for technical meetings to Cadence sites outside the US.
Cadence is the global leader in software, hardware, and services that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs and with higher quality.
Cadence is an equal opportunity employer and is committed to hiring a diverse workforce.